Devconf.cz 2023

I am coauthor and lecturer of the Computer Architectures source at Czech Technical University in Prague, Faculty of Electrical Engineering. We have based our course on the book Computer Organization and Design, The HW/SW Interface written by professors Patterson and Henessy. We have switched our education from MIPS to RISC-V architecture, implemented own simulator for education, in he first iteration the MIPS based, in actual RISC-V based. Simulators online versions, pointers to their source repositories and to the courses materials and recordings are available at https://comparch.edu.cvut.cz/ . We work even on VHDL model matching the educational 5-stage pipeline RISC-V design which is focussed on demonstration in GHDL simulator. It has been successfully tested even on Intel and AMD/Xilinx FPGAs but there is no intention to make it usable for production application, i.e. optimal and pipeline balanced, goal is to match educational model. We participate in RISC-V International Academic and Training Special Interest Group as well so we can help to build contacts and join forces.